1. Field of Invention
This invention relates to surface laminated circuit (SLC) components, and methods of manufacture. More particularly, the invention relates to spacer-connector studs for stacked SLC multi chip modules and methods of manufacture.
2. Description of Prior Art
A Surface Laminated Circuit (SLC) printed circuit board has successively laminated copper clad glass-epoxy laminations as a substrate. A photosensitive epoxy resin serves as an insulating layer and a copper plated layer as an external-conducting surface. SLC type circuit boards are described in U.S. Pat. No. 5,766,825 assigned to the assignee of the present invention and fully incorporated herein. Electronic components, e.g Random Access Memory (RAM); Read Only Memory (ROM); Integrated Circuits (IC), etc. may be modularized and attached to the Lipper and lower surfaces of the SLC board by solder ball reflow joininig techniques. The attached modules may be interconnected through the conductive layer of the upper and lower surfaces of the board.
It is desirable to stack the SLC boards to save component space and shorten the signal paths between the boards. The stacked array of boards requires that the boards be positively spaced apart to prevent contact of the components attached to the board. Moreover, signal paths of the boards must be interconnected without disturbing any of the solder ball connections between components and the SLC boards. The spacing and interconnecting of the boards must be inexpensive and suitable for assembly line manufacture What is needed in the art is a component, which serves as a spacer for separating the SLC boards and at the same time providing a dense array of signal paths that can be routed through the spacer for interconnecting the modules on the spaced SLC boards.
Prior art related to stacked multi-chip modules includes:
U.S. Pat. No. 6,014,313 entitled xe2x80x9cPackaging Structure for Integrated Circuitsxe2x80x9d by H. Hesselbom, issued Jan. 11, 2000 discloses a three-dimensional multi-chip module formed as a s%tack of two-dimensional multi-chip modules comprising substrates which have electrically signal paths connecting integrated circuit chips and has vertical interconnections of the signal paths, provided by interconnection or via chips. The individual chips or other inner components on a substrate are in mechanical contact with a surface of an adjacent substrate and constitute the distance device maintaining the substrates spaced from each other. Thus heat developed in components can be conducted essentially perpendicularly to the substrates. Thermally conducting chips can be used for improving the conducting of heat. Cooling devices are located only at the top and bottom surfaces of the stack. Channels are formed between the chips and components which can be used for cooling and furthermore spaces are formed at the edges of the substrates in which electrical connectors can be inserted for coupling the stack to a similar stack, since there are no cooling devices at the lateral surfaces of the stack. The components of the stack are maintained in a detachable manner in electrical and mechanical contact with each other by applying a compressive force and by using elastic connecting and guiding devices. In particular bumps can be arranged cooperating with edge surfaces of components to guide components to correct positions.
U.S. Pat. No. 5,130,894 entitled xe2x80x9cThree-Dimensional Circuit Modulesxe2x80x9d by W. H. Miller, issued Jul. 14, 1992 discloses a three-dimensional circuit structure particularly useful in semiconductor memories. The circuit structure consists of a stack of modules mounted on a motherboard with connectors between adjacent modules in the stack. The connectors mate with staggered and through terminals on the modules; the staggered terminals being used for circuits routed to destinations on specific modules and the through terminals for circuits routed to destinations on more than one module.
U.S. Pat. No. 5,111,278 entitled xe2x80x9cThree-Dimensional Multi-Chip Module Systemsxe2x80x9d by C. W. Eichelberger, issued May 5, 1992 discloses a multichip integrated circuit packages and methods of fabrication, along with systems for stacking such packages. In one embodiment, the multichip package has an array of contact pads on an tipper surface thereof and an array of contact pads on a lower surface thereof. Connection means are provided for electrically coupling at least some of the contact pads on each package surface with selected ones of the contact pads on the other surface, or selected interconnection metallization which is disposed between integrated circuits located within the package. The contact pads of each surface array are preferably equal in number and vertically aligned such that multiple multichip packages may be readily stacked, with a conductive means disposed therebetween for electrically coupling the contact pads of one package to the pads of another package. In addition, various internal and external heat sink structures are provided which facilitate dissipation of heat in a multichip package or in a stack of multichip packages.
None of the prior art discloses a stacked array of SLC multi-chip modules including a spacer and interconnector comprising at least two glass-epoxy dielectric laminates with interconnecting circuit patterns for spacing and interconnecting the SLC multi-chip modules without disturbing any of the existing connections between the multi-clip modules and the SLC boards.
A stacked array of multi-chip modules cards are interconnected through a surface laminated stud which serves as an interconnector and spacer for the stacked multi-chip modules cards. The stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. A circuitization pattern is formed in the copper layer by selected etching. Drilled and plated through holes within the laminates can carry many signals between laminates plus power and ground lines. A photosensitive thermal-setting resin insulating layer is applied atop the wiring layer. The resin-insulating layer is formed by applying a solution of soluble photosensitive, thermal-setting resins in a solvent atop the wiring layer. The solvent resins are evaporated by a pre-cure heating. The heating step serves to drive off the solvent and solidify the resins"" insulating layer. The resin layer is planarized by abrasion. The top and bottom laminates of the stud may include a spatial array of thermal contacts suitable for C4 bump technology. A location is selected on the card to accommodate the laminated stud. The thickness of the stud is greater than twice the thickness of the components attached to the card The thermal contacts on the stud, typically solderable, join to the circuit patterns on the multi-chip module card. A second multi-chip module card having components on top and bottom surface is mechanically aligned and pressed against the contacts on top surfaces of the stud to form an assembly. The assembly can be heated causing the second card to become soldered to the contact footprint on the stud. A solder hierarchy may be employed such that overlying circuit board and stud does not reflow when the bottom surface of the stud is joined to the underlying circuit board.